With the rapid development of various mobile systems and other applications, the importance of flash memories as nonvolatile storage device is increasing. Flash memories are advantageous to use in terms of high data storage capacity. However, compared to random-access memories, flash memory devices are relatively slow during read and write operations, and this may affect the performance of systems employing them.
The long access time of flash memories may be compensated by using buffer memories. For instance, data to be transferred from a host to a flash memory is first stored in a buffer memory; then the data is written from the buffer memory to the flash memory. Similarly, data read from the flash memory may be first stored in the buffer memory and then the data may be transferred to the host. With such a data transmission scheme, it is possible to enhance the performance of memory systems and/or information processing systems.
One type of flash memory device employs a NAND-type memory cell array with a NOR-type interface to retain the benefits of NAND memory while providing the higher access speeds of NOR-type flash memory. An example of such a hybrid device, which will be referred to herein as NOR-NAND memory, is Samsung's OneNAND® brand flash memory. NOR-NAND flash memory devices have the buffer and flash memories integrated on a single chip along with a control logic block. Such a prior art NOR-NAND flash memory device is schematically illustrated in FIG. 1.
Referring to FIG. 1, the NOR-NAND flash memory device 1000 executes read and write operations in response to requests from a host 2000. The NOR-NAND flash memory device 1000 includes a nonvolatile memory core 1200, a buffer memory 1400, and a control block 1600. The nonvolatile memory core 1200 includes a nonvolatile memory cell array 1220 and a page buffer 1240, being regulated by the control block 1600. The page buffer 1240 reads page data (i.e., data corresponding to a quantity of one page) from the nonvolatile memory cell array, and temporarily stores the readout data therein. The buffer memory 1400 is configured to conduct the read and write operations under the control of the control block 1600, temporarily holding the page data output from the nonvolatile memory core 1200. The buffer memory 1400 is designed to sufficiently accommodate the page data. The buffer memory 1400, for example, may be a static RAM (hereinafter, referred to as “SRAM”). The page data are sequentially transferred to the host 2000 from the buffer memory 1400 in a unit in sync with a clock signal.
FIG. 2 is a schematic block diagram illustrating the prior art buffer memory 1400 of FIG. 1. Referring to FIG. 2, the buffer memory 1400, which may be an SRAM, includes a memory cell array 1410, a row selection circuit 1420, a column selection circuit 1430, a sense amplifier circuit 1440, and a data output circuit 1450. The row selection circuit 1420 activates wordlines WLi (i=0˜m−1) in sequence when the read operation begins. When each wordline is selected, bitlines BLj (j=0˜n−1) of the memory cell array 1410 are designated by the column selection circuit 1430 in a regular unit. The sense amplifier circuit 1440 detects and latches data bits through the bitlines designated by the column selection circuit 1430. The data output circuit 1450 outputs data bits to an external device from the sense amplifier circuit 1440. The buffer memory 1400 stores a quantity of one page of data (i.e., page data). The page data stored in the buffer memory 1400 are stored in memory cells of plural rows (i.e., the memory cells of all rows included in the memory cell array 1410), rather than the memory cells of a single row.
An SRAM, when used as the buffer memory 1400, sequentially performs address decoding, wordline activation, column decoding, bitline sensing, data latch on bitlines, and wordline deactivation in one cycle of a clock signal. When a selected row is deactivated, another row is activated after precharging the bitlines. A wordline is fixed in active-inactive and precharging periods. If the data transfer rate (or the data burst frequency) from the buffer memory to the host increases, the period A shown in FIG. 3 decreases. When the data burst frequency is increased to achieve a higher data transfer rate, it is more difficult to assure that the precharge time can be completed during period A. In other words, the precharging operation, which needs to be carried out every clock cycle, acts to restrict elevation of the data transfer rate (or the data burst frequency) from the buffer memory 1400 to the host 2000.